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  pt0137(08/04) ver:4 1 data sheet PT8R1202 pt pericom technology inc. bluetooth digital audio streaming ic ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| features y compliant to bluetooth specification v1.2 y seamless interface to pt8r1002 (bluerf? rf transceiver) y high speed uart, usb 1.1 interface with hub/devices and host function, up to four channels 8khz pcm / cvsd codec, 16/18/20/24-bit i 2 s audio input/output and spdif input/output interface, 2 channel digital amp interface y integrated 128mhz pti own hybrid risc and dsp picoii embedded processor with 24-bit multiplication and 48-bit accumulation and 128kbyte on-chip sram enough to support several digital audio and speech codecs y on-chip implementation of bt qualified link controller, link manager, hci, l2cap, rfcomm and several profiles such as headset, spp, obex, av profiles, etc. y software development kit and source code licenses available for qualified embedded stacks and dsp firmware for popular digital audio and speech codecs y single reference clock for system, usb, audio sub system y 0.18um cmos technology application y bluetooth portable audio players y stereo audio headset with hsp/hfp function y multi-functions usb dongle such as bluetooth, usb audio device, usb flash storage, etc. y wireless high quality digital audio streaming system for dvd/pc speaker general descriptions the PT8R1202 is a part of the pti bluetooth product family. it is a dsp processor with the functionality of both baseband controller providing the bluetooth? functionality for high data rate, short-distance wireless communication in the free 2.4ghz ism band and digital audio decoder such as mp3 or ac3. together with pt8r100x 2.4ghz radio transceiver ic and an external flash memory, it provides a fully compliant bluetooth system for data and voice communications. PT8R1202 consists of bluerf? rxmode2/3, 3-wires radio interface, bluetooth? baseband and bit processor, pti proprietary 32-bit hybrid risc/dsp embedded processor with 48bit resolution, and usb / uart / pcm / dac / i2s / spdif / smc standard interfaces. the on-chip 32-bit hybrid risc/dsp embedded processor is powerful enough to support full rate bluetooth data communications as well as full rate digital audio decoding and includes large enough embedded sram up to 128kbyte to support several applications without external memory, which results in cost-effective and low-power consumption systems. in combination with pti own optimized bluetooth? baseband, embedded protocol stacks and audio decoder firmware, it provides a complete cost-effective soc embedded solutions such as portable mp3 decoder, wireless high quality speaker system or headset.
pt0137(08/04) ver:4 2 data sheet PT8R1202 pt pericom technology inc. bluetooth digital audio streaming ic ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ordering information package device type size shipment method order number tray PT8R1202f normal t&r PT8R1202fx tray PT8R1202fe lqfp144 pb(lead) free 20 x 20 x 1.4mm t&r PT8R1202fex tray PT8R1202nd normal t&r PT8R1202ndx tray PT8R1202nde PT8R1202 fpbga144 pb(lead) free 10 x 10 x 1.4mm t&r PT8R1202ndex block diagram hybrid 32 -bit risc mcu & 24-bit dsp core (v6@picoii -dsp,128mhz) mem if multi-mode rf transceiver i/f (bluerf rxmode2/3 3-wires rf i/f) interrupt / timer bluetooth controller bit processor (bt1.2 compliant) xmem0 32kb 20bit address, 16bit data i/o0 (2mb) (lcd) sram (2mb) (option) flash (2mb) mmu & dma v6pb bridge power mng . speech codec i/f serial speech codec system registers ymem0 32kb xmem1 16kb ymem1 16kb i-cache 16kb xmem2 16kb ymem2 16kb stereo audio dac serial bluetooth radio pt8r1002 syspll osc osc 12/13/16/19.2mhz serial jtag serial host, off-chip debugger pc phone pda usb (multi-function devices or host) bluerf rxmode2 high speed uart nand nand flash (2x2gb) nand flash controller audpll i2s input, spdif input stereo audio adc on - chip debugger gpio (up to 56) rtc serial i/o1 (2mb) (ide/ ethernet) rtos (vpos ?, ecos ?) bb/lm hci pti stacks & profiles third party stacks & profiles dsp library network library file system library user applications PT8R1202 software osc 32.768khz i2s output, spdif output gpio
pt0137(08/04) ver:4 3 data sheet PT8R1202 pt pericom technology inc. bluetooth digital audio streaming ic ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| product description bluetooth is an open specification for short-range data communications. it operates in the globally available 2.4 ghz to 2.5 ghz ism free band. fast frequency hopping (1600 hop/s), 79 available channels (2.402 to 2.480 ghz), and a maximum 1 mbit/s gfsk modem are allowed. the PT8R1202 consists of a bluetooth baseband hardware, on-chip 128mhz hybrid embedded risc / dsp processor and peripheral interface block. the PT8R1202 focuses on audio streaming to distribute audio content of high-quality in mono or stereo on acl channels of bluetooth. since PT8R1202 is highly integrated soc solution to support the advanced audio distribution profile(a2dp) defined in bluetooth as audio streaming application with minimum bom, the minimum required external devices are just pt8r100x 2.4ghz radio transceiver ic, external antenna, crystal, and minimum 256kb flash memory for program code. bluetooth baseband hardware bluetooth baseband hardware consists of modem control, packet processing hardware, and on-chip microcontroller interface. modem control part generates the control signal for modem and rf block and transmits or receives data with modem. PT8R1202 supports bluerf? rxmode2/3 bluetooth radio interface with uni/bi- directional and jtag/dbus serial interface like pt8r1000 or pt8r1001 pti bluetooth radio transceiver. in rxmode3, syncword correlator is located in radio transceive r, syncword detect signal feeds from external radio transceiver. in rxmode2, syncword correlation is processed in PT8R1202, syncword detect signal feed to external radio transceiver to timing adjustment of modem. in additional to bluerf? interface, PT8R1202 supports blueq? interface with sbi serial interface. packet processing for bluetooth is implemented by a dedicated hardware for a low power solution whilst providing the required data throughput. the function implemented in hardware include : forward error correction, header error control, cyclic redundancy check, encryption, and data whitening. on-chip microcontroller interface generates interrupt signal to on-chip interrupt handler and processes dma operation with 16kb internal memory(xmem2) which is shared with on-chip microcontroller. during radio transmission this block constructs a packet from head er information and payload data/voice taken from a ring buffer in xmem2 which is previously loaded by softwa re. for radio reception, this block stores the packet header and the payload data in the appropriate ring buffer in xm em2, which is indicated by software. after the completion of reception, this block generates interrupt signal to on-chip interrupt handler. this architecture minimizes the in terventions required by the processor during packet transmission and reception. hybrid embedded risc / dsp processor to satisfy multimedia data streaming through wireless connectivity like bluetooth, the embedded processor used in portable system must prov ide highly energy-efficient operations, due to the importance of battery weight and size without compromising high performance when the user requires it. the functions required in this application are classified into two computations such as mcu operation and dsp operation. the form er performs all functions associated with user inte rface as well as real-time communication protocols and the latter performs all signal- processing and multimedia functions. the on-chip embedded processor in the PT8R1202 is based on pti proprietary v6 processor(picoii-risc/dsp), which is optimized to accel erate both two computations for low power and high performance embedded processing. its instruction set is optimized not only for general embedded processing but also dsp signal processing specially used in audio and speech code. this hybrid embedded risc/dsp processor supports 24-bit multiplication and 48-bit accumulator with dsp functionality such as saturation and rounding. also, it supports simd features, which results in high performance in 16- bit speech applications. to support low power consumption, on-chip processor adopts programmable dynamic clock control, reduces the complexity of embedded rtos optimizing for both bluetooth connectivity and audio streaming, and minimizes external i/o access with several techniques. default operation frequency is 96mhz at boot and it can be increased to 128mhz entering into turbo mode. there are four global power states provided in PT8R1202 such as active state, sleep state, deep sleep state and po wer-off state. in active state, processor can change the processor clock between normal operation clock, a half of one, and a third of one. for example, if processor operates in turbo mode, it can change processor clock between 128mhz, 64mhz and 42mhz. also, during the execution of ?idle? instruction, it cuts down the processor clock without interrupting i/o device operation. in sleep stat e, the clock of all processor and i/o device except rtc is disabled. in sleep state, processor can be waked up quickly by rtc time-out event or external trigger signal since on-chip pll is still working in order to fast response. deep sleep state is the same of sleep state except on-chip pll is off also. since on-chip pll is off in deep sleep stat e, the power consumption is reduced very much but requires more latency during wake- up. to minimize the access of external flash memory for code, PT8R1202 includes on-chip 16kb instruction cache. in addition to instruction cache , frequent access code or time critical code is dynamically located on scratch-pad memory of internal x/ymem region. it is possible to allocate up to 96kb as scratch-pad memory in order to reduce external memory access for low power and high performance bluetooth digital audio streaming system. total 128kb internal sram is integrated large enough to support both on-chip bluetooth stack and audio application without external memory, which results in cost-effective and low-power consumption systems. internal sram
pt0137(08/04) ver:4 4 data sheet PT8R1202 pt pericom technology inc. bluetooth digital audio streaming ic ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| consists of six types memories : xmem0, xmem1, xmem2, ymem0, ymem1, and ymem2. all memories can be byte accessible as general purpose data memory. some memories such as xmem2 and ymem2 have special usage. xmem2 is used as 16kb memory for communication with bluetooth baseband hardware or usb, and ymem2 is used as 16kb memory for communication with audio data buffer for stereo pcm output. PT8R1202 can boot from nor type flash and nand type flash memory. with nor type flash memory, code can be cached into internal instruc tion cache in order to execute code at high frequency and reduce power consumption of frequent memory fetch. with nand type flash memory, both code and data are stored same memory, which results in the reduction of system bom and form factor. if PT8R1202 boots from nand flash, the configuration of the internal instruction cache is optimized to support nand flash efficiently. software development environment the PT8R1202 supports high-level programming development with our optimized c compiler based on gcc and intrinsic library functions to maximize the software development productivity. the system software to support application software development includes c-compiler, multi-level instruction set simulator, performance analyzing profiler, memory configuration optimizer and power monitor. specially, our c compiler supports automatically collaboration mechanism between compiled general code and hand-written dsp libraries to maximize the utilization of v6 advanced features. to reduce the system developing cost, pti provides performance optimized dsp library for enabling several multimedia standards with our own developing skill for multimedia application. this library supports several standards such as mpeg-1/2 layer i, ii, iii audio decompression, dolby digital decompression, wma, sbc codec, g.723.1/g.728 speech codec, etc. advanced audio streaming on bluetooth PT8R1202 supports advanced audio streaming using the advanced audio distribution profile(a2dp) defined in bluetooth. this profile is used by devices to distribute audio content of high-quality in mono or stereo on acl channels, as well as bluetooth audio which indicates distribution of narrow band voice on sco channel. PT8R1202 support several codecs in a2dp such as low complexity subband codec(sbc), mpeg-1,2 audio, or wma. this advanced audio streaming feature of PT8R1202 can be used several audio system with bluetooth connectivity between portable audio player and headphone, high-quality audio system and surround speaker, or portable speech recorder and microphone. for supporting a2dp, PT8R1202 embeds all bluetooth stack such as baseband, lmp, l2cap, sdp, avdtp(a/v distribution transport protocol) and avctp(a/v control transport protocol). as well as a2dp, PT8R1202 supports cordless phone or dial-up networking using rfcomm, tcs/bin protocol and profiles. peripheral interface block PT8R1202 has several peripheral interface such as off-chip memory interface, usb inte rface, uart interface, pcm interface, i2s and spdif inte rface, jtag interface, flash memory/card interface, and up-to 59-general purpose programmable i/o(gpio) interf ace. all peripheral devices are connected to on-chip mi crocontroller via internal peripheral bus(v6pb), which is compatible with advanced peripheral bus(apb) from arm? off-chip memory interface suppo rts 4 devices concurrently such as flash memory, sram, an d i/o for code and data. it supports 2mb address space an d 16bit data with byte access functionality. the access timi ng for each device can be programmable by software. also, PT8R1202 supports external i/o with explicit wait signal such as pcmcia card. usb interface supports both 12mbps and 1.5mbps serial data communication conforming to universal serial bus standard version 1.1. it supports both device and host side operation and all operation modes such as bulk, interrupt, control and isochronous mode. it consists of one control end-point, four receiver end-points and four transmit end- points, each of which has dual 64bytes fifo except control end-point and supports bulk, interrupt, and control, and two pair of end-points which supports isochronous mode up to 1023bytes. on-chip uart supports programmable baud rate up to maximum 1.84mbaud serial communication and fully programmable serial interface such as flow control and bit format. it includes separate 16-byte transmit and receiver fifos to reduce cpu interrupts. pcm interface supports the external pcm codec with cvsd bluetooth codec functionality. for the external pcm codec, it support 8-bit a/u-law pcm and 13- or 14-bit 8khz linear pcm in both master or slave mode. for 8-bit a/u-law format, it supports one, two and four channels simultaneously. audio output interface supports i2s digital audio interface, spdif digital audio interface. for external dac, it supports 32, 44.1, or 48khz sampling frequencies with the programmable bit resolution up to 24bit. all sampling frequency can be generated both from on-chip audio pll or external clock source. audio input interface supports both i2s interface and spdif interface with 32, 44.1, or 48khz sampling frequencies. for slave mode in which all control signals come from external, i2s interface can support up to 192khz sampling frequency. PT8R1202 supports the dedi cated hardware interface to smartmedia? flash memory(nand type) or card. without the occupation of the cpu resource, it supports dma transfer for smartmedia? interface to achieve fast read/write operation. at smc boot mode, PT8R1202 can boot from smc without normal parallel flash of nor type. PT8R1202 provides 59-bit programmable, bi-directional io(gpio) which are shared with dedicated pins in order to reduce pins. gpio signal can be used as key-pad input, mmc/sdcard/memory stick? interface, or lcd interface.
pt0137(08/04) ver:4 5 data sheet PT8R1202 pt pericom technology inc. bluetooth digital audio streaming ic ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| PT8R1202 supports standard jtag interface for both boundary scan and communication channel with pti enhanced on-chip hardware debugger controller. using on- chip debugger controller, off-chip debug handler or external host can access internal peripher al device registers, external memory interface, and executes real-timing hardware debugging and monitoring of on-chip embedded risc processor. also, external host can communicate on-chip processor through jtag with on-chip hardware managed channel buffer.
pt0137(08/04) ver:4 6 data sheet PT8R1202 pt pericom technology inc. bluetooth digital audio streaming ic ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| pin descriptions pin name pin i/o type description di(digital input, 3.3v), do(d igital output, 3.3v), db(digital bidirectiona l, 3.3v), dp(digital programmable, 3.3v) dcp(digital core power, 1.8v), dpp(digital peripheral power, 3.3v) dcg(digital core ground), dp g(digital peripheral ground) aai(analog audio input, 3.3v), aao(analog audio output, 3.3v), aab(analog audio bidirectional, 3.3v) aci(analog core input, 1.8v), aco(analog core output, 1.8v), acb(analog core bidirectional, 1.8v) aap(analog audio power, 3.3v), aag(analog audio ground) acp(analog core power, 1.8v), acg(analog core ground) bluetooth interface : 12 txactive / gpa[0] d4 do/ dp active high transmitter enable rxactive / gpa[1] c1 do / dp active high receiver enable txdata_en / gpa[2] e2 do / dp active high timing referenc e of valid data txdata / gpa[3] d1 db / dp serial data transmit data rxdata / gpa[4] e3 di / dp serial data receive data syncdectect / gpa[5] e1 db / dp active high indication of sync word detection dataclk / gpa[6] f1 di / dp clock phy reference data clock rfreset / gpa[7] f3 do / dp active high reset signal for external radio transceiver bluerf_tck / gpa[8] f2 do / dp clock a serial register interface clock bluerf_tms / gpa[9] g3 do / dp serial da ta control signal of phy?s tap controller bluerf_tdi / gpa[10] g1 db / dp serial data phy control re gister serial data output bluerf_tdo / gpa[11] g2 di / dp serial data phy control register serial data input clock signal interface : 6 xtalin j8 di clock crystal input for on-chip pll (see note1) xtalout l9 do clock crystal output pll_md1 m10 di control pll mode contro l (see note1) external, test clock input (see note1, 2) pll_md0 m11 di / do control pll mode contro l (see note1) manufacturing test mode (see note2) pllsel l10 di control pin external cloc k source select signal (see note1,2) clkout / gpb[0] l7 do / dp clock clock out divided by a third of internal system clock (see note1) test & debug interface : 9 reset k8 di active low reset signal btmd[1:0] m7, j7 di / dp control pin boot mode (see note2) scan_en c5 di control pin manufacturing test (see note3) jtag_tck / gpc[4] m8 di / dp clock jtag clock signal jtag_tms / gpc[5] k7 di / dp se rial data jtag te st mode signal jtag_rst / gpc[6] l8 di / dp active low jtag reset signal jtag_tdi / gpc[7] k9 di / dp seri al data jtag serial input data jtag_tdo / gpc[8] m9 do / dp serial data jtag serial output data external memory interface : 45 mema[19:0] (see note4) do bus address bus for external memory memd[15:0] (see note5) db bus data bus for external memory web c10 do active low write enable signal for external memory reb c12 do active low read enable signal for external memory ube / gpb[1] d11 do / dp active low upper byte enable (see note6) lbe / gpb[2] d10 do / dp active low lower byte enable (see note6) flashcsb / gpb[3] d12 do active low chip select for external flash memory sramcsb / gpb[4] e10 do / dp active low chip select for external sram memory iocsb0 / gpb[5] e11 do / dp active low chip select for external i/o device0 iocsb1 / sm_csb1 / gpb[6] e12 do / dp active low ch ip select for external i/o device1 (see note7) iowait / gpb[7] f10 di / dp control pi n io wait cycle extension indication signal uart & usb interface : 6 uarttx / gpc[0] h3 do / dp serial data uart serial transmit data / usboe uartrx / gpc[1] h1 di / dp serial data uart serial receive data / usbspeed digamp_l / uartrts / audisclk / gpc[2] h2 do / dp active low uart rts(ready to send) signal / usbvpo audisclk / digamp_l (see note8) digamp_r / uartcts / audilrclk / gpc[3] j4 do / dp active low uart cts(clear to send) signal / usbvmo audilrclk / digamp_r(see note8) d+ b4 db serial data usb d+ d- a4 db serial data usb d-
pt0137(08/04) ver:4 7 data sheet PT8R1202 pt pericom technology inc. bluetooth digital audio streaming ic ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| pin name pin i/o type description digital audio interface : 9 pcmout / gpd[0] j3 do / dp se rial data pcm 8kbps data out pcmin / gpd[1] j1 di / dp serial data pcm 8kbps data input pcmsync / gpd[2] j2 dp clock pcm 8khz frame synchronization signal pcmclk / gpd[3] k1 dp clock pcm bit data clock (128/256) audsclk / gpd[4] k2 dp clock audi o serial data bit clock(64*fs) audlrclk / gpd[5] l1 dp clock/ a udio left/right sync clock(fs) audout / gpd[6] l2 do / dp serial data audio seri al data output audmclk / gpd[7] m1 dp clock a udio oversampled clock(256/384*fs) audin / spdifin/gpd[8] k3 di / dp seri al data audio serial data input analog audio interface : 6 (see note9 ) mic_in b2 aai analog reserved micgs a1 aao analog reserved vmid c3 aao analog reserved vref c2 aao analog reserved eara c4 aao analog sleep crystal(32.768khz) xtalin earb b1 aao analog sleep crystal(32.768khz) xtalout smartmedia interface : 14 sm_csb / gpe[0] l3 do / dp active low smartmedia chip select sm_cle / gpe[1] m2 do / dp active low smartmedia command latch enable sm_ale / gpe[2] m3 do / dp active low smartmedia address latch enable sm_we / gpe[3] k4 do / dp active low smartmedia write enable sm_oe / gpe[4] m4 do / dp active low smartmedia read enable sm_rb / gpe[5] l4 di / dp control pin smartmedia ready signal sm_data[7:0] /gpf[7:0] (see note10) db bus smartmedia data/address bus gpio interface : 7 gpg[0] / irq0 / ssm1 d6 di / dp active high external interrupt request0 (see note11) gpg[1] / irq1 b6 di / dp active high external interrupt request1 / usbvpi gpg[2] / wakeup c6 di / dp active high exte rnal wake up signal (see note12) / usbrcv gpg[3] / ssm0 a5 do / dp clock size indicator at smartmedia boot (s ee note11) / usbvmi gpg[4] / clk32k d5 db / dp signal extern al rtc clock(32khz) input (see note13) spdifo / gpg[5] b5 do / dp signal spd if output / usbsuspnd (see note14) power supplies : 31 spll_vcc(1) l11 acp power supply for system pll (1.8v) spll_gnd(1) m12 acg ground ground for system pll apll_vcc(1) d3 acp power supply for audio pll (1.8v) apll_gnd(1) d2 acg ground ground for audio pll acodec_vcc(1) a2 aap power supply for combo audio codec (3.0v) acodec_gnd(2) a3, b3 aag ground ground for combo audio codec vcc(6) (see note15) dcp power power for digital core block (1.8v) vcc_gnd(6) (see note16) dcg ground ground for digital core block vpp(6) (see note17) dpp power supply for digital peripheral blocks (3.3v) vpp_gnd(6) (see note18) dpg ground ground for digital peripheral blocks note : 1. PT8R1202 use two main clocks for core operation and peripheral operation. both clocks can be generated from on-chip pll or individually pumped from external clock source. the clock for pro cessor operation, named clksys, can be variable by application requirement or dynamic power ma nagement, but the clock for peri pheral operation must be fixed as 48mhz for usb and audio interf ace and 32mhz for others. the pll in the PT8R1202 supports 12mhz, 13m hz, 16mhz, or 19.2mhz as reference clock. following table shows the configuration of PT8R1202 clock generation block. for usi ng internal clock from on-chip p ll, pllsel must be set ?0?. when using internal clock from on-chip pl l, PT8R1202 can change the op erating frequency of on-chip processor up to 128mhz turbo mode. the default operation mode is normal execution at 96mhz operating fr equency and it can be changed into turbo mode by soft ware. however, in the case of using external cl ock source, it does not support turbo mode.
pt0137(08/04) ver:4 8 data sheet PT8R1202 pt pericom technology inc. bluetooth digital audio streaming ic ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| table 1. pll mode set valu e for setting core frequency xtalin pll_md1 pll_md0 pllsel clkout clksys comment 32mhz 96mhz normal mode 12mhz low low low 42.7mhz 128mhz turbo mode 32mhz 96mhz normal mode 13mhz low high low 42.7mhz 128mhz turbo mode 32mhz 96mhz normal mode 16mhz high low low 42.7mhz 128mhz turbo mode 32mhz 96mhz normal mode 19.2mhz high high low 42.7mhz 128mhz turbo mode don?t use 96mhz low high 32m hz 96mhz normal mode don?t use testclk high high testclk testclk test mode 2. if both pll_md0 and pllsel are high, the operation mode of pt 8r1202 changes into test mode. th is mode is used only for manufacturing test purpose. in test mode, the boot mode will be used as indication of specific test mode. in normal mode, the b oot mode indicates the source of boot code to be fetched first pc. table 2. boot mode set value fo r indicating the source of boot code fetch in normal mode btmd[1:0] name comment 0 flash boot from external memory using flashcsb[0] signal 1 debug wait for debug command through jtag 2 reserved 3 nandflash bood from nandflash using smart media interface the size of nandflash is indicated by ssm pin. see note7 for more information. table 3. boot mode set value fo r indicating the source of boot code fetch in test mode btmd[1:0] name comment 0 scan test full scan test mode (manufacturing test purpose) 1 codec test analog audio external test mode (debugging purpose) 2 codec0 test audio left dac and adc test mode (manufacturing test purpose) 3 codec1 test audio right dac and adc test mode (manufacturing test purpose) 3. this pin should be low for normal operation. it is used only in manufacturing test. 4. pin of mema[19:0] : a6, b7, a7, c7, d7, b8, a8, d8, a9, c8, d9, a10, b9, c9, b10, a11, a12, b11, b12, c11 5. pin of memd[15:0] : f11, f12, g11, g12, h12, g10, h11, h10, j12, k12, j9, j11, j10, l12, k11, k10 6. in non byte access device such as flash me mory(x16), these pin will be not connected. 7. this pin can be programmed to access the second nand flash chip in addition to sm_csb signal. with this pin, PT8R1202 can suppo rt up to 4 gb(512mb) nand flash directly. 8. these pins can be used as mu ltiple purposes by programming such as digital am p output, uart flow control signal and alternative i2s input. from r2.4, the default direction and signal usage is changed. the default configuration is the output of internal digita l amplifier. for the case of alternative i2s input mode, the sampling frequenc y of i2s input can be different to that of i2s output. 9. internal audio codec is not recommended to use for both voice and audio. instead of internal stereo sigma-delta dac, we recomme nd to use external voice and audio codec. from r2.6, eara and earb p ad are only dedicated to oscillator pad for external sleep crysta l. 10. pin of sm_data[7:0] : k5 , j5, m5, l5, k6, m6, j6, l6 11. these pins is only used at nandflash boot mode. if btmd is ?11? which means on-chip processor boots from nandflash, these p ins are used as size indication of external nandfla sh. after the completion of boot, it is used as gpio. otherwise, it is always used a s gpio. 12. this signal can be programmed for embedded processor to be waked up from sleep or deep sleep power state. 13. instead of dividing clock from xtalin, this pin can be used as the low oscillator clock source as programming for extremely low power consumption in stand-by state. 14. from r2.4, the default direction of th is pin is output as spdif output signal. 15. pin of vcc : g4, h4, h5, h6, h7, h8 16. pin of vpp : f5, f6, f7, f8, g9, h9 17. pin of vcc_gnd : e4, f4, g5, g6, g7, g8 18. pin of vpp_gnd : e5, e6, e7, e8, e9, f9
pt0137(08/04) ver:4 9 data sheet PT8R1202 pt pericom technology inc. bluetooth digital audio streaming ic ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| package diagram the circuits is packaged with 144pin fpbga and lqfp package. the body size of fpbg a is 10x10mm and the body size of lqfp is 20x20mm. following figure shows the top view of the package. micgs earb gpa1 gpa3 gpa5 gpa6 gpa10 gpc1 gpd1 gpd3 codec vcc micin vref apll gnd gpa2 gpa8 gpa11 gpc2 gpd2 gpd4 codec gnd codec gnd vmid apll vcc gpa4 gpa7 gpa9 gpc0 gpd0 gpd8 d- d+ eara gpa0 vcc gnd vcc gnd vcc vcc gpc3 gpe3 gpg3 gpg5 scan en gpg4 vpp gnd vpp vcc gnd vcc gpf6 gpf7 ma19 gpg1 gpg2 gpg0 vpp gnd vpp vcc gnd vcc gpf1 gpf3 ma17 ma18 ma16 ma15 vpp gnd vpp vcc gnd vcc btmd0 gpc5 ma13 ma14 ma10 ma12 vpp gnd vpp vcc gnd vcc xtal in rst ma11 ma7 ma6 ma9 vpp gnd vpp gnd vpp vpp md5 gpc7 ma8 ma5 web gpb2 gpb4 gpb7 md10 md8 md3 md0 12 345678910 a b c d e f g h j k 10mm 10mm ma4 ma2 ma0 gpb1 gpb5 md15 md13 md9 md4 md1 11 ma3 ma1 reb gpb3 gpb6 md14 md12 md11 md7 md6 12 gpd5 gpd6 gpe0 gpe5 gpf4 gpf0 gpb0 gpc6 xtal out pll sel l spll vcc md2 gpd7 gpe1 gpe2 gpe4 gpf5 gpf2 btmd1 gpc4 gpc8 pll md1 m pll md0 spll gnd ? mic_in ? acodec_vcc ? acodec_gnd ? acodec_gnd ? d+ ? d - ? dig vpp ? dig gndp ? scan_en ? mmc_data(gpg[5]) ? mmc_cmd(gpg[4]) ? mmc_clk(gpg[3]) ? wakeup(gpg[2]) ? irq1(gpg[1]) ? irq0(gpg[0]) ? mema19 ? mema18 ? mema17 ? mema16 ? mema15 ? mema14 ? dig vcc ? dig gndc ? mema13 ? mema12 ? mema11 ? mema10 ? mema9 ? mema8 ? mema7 ? mema6 ? mema5 ? dig vpp ? dig gndp ? mema4 ? mema3 PT8R1202-qfp144 audmclk(gpd[7]) audin(gpd[8]) dig gndp dig vpp sm_csb(gpe[0]) sm_cle(gpe[1]) sm_ale(gpe[2]) sm_we(gpe[3]) sm_oe(gpe[4]) sm_rb(gpe[5]) sm_data7(gpf[7]) sm_data6(gpf[6]) sm_data5(gpf[5]) sm_data4(gpf[4]) sm_data3(gpf[3]) sm_data2(gpf[2]) sm_data1(gpf[1]) sm_data0(gpf[0]) dig gndc dig vcc btmd0 btmd1 clkout(gpb[0]) reset jtag_tck(gpc[4]) jtag_tms(gpc[5]) jtag_rst(gpc[6]) jtag_tdi(gpc[7]) jtag_tdo(gpc[8]) xtalin xtalout dig gndp dig vpp pll_sel pll_md1 pll_md0 ? 1 ? 2 ? 3 ? 4 ? 5 ? 6 ? 7 ? 8 ? 9 ? 10 ? 11 ? 12 ? 13 ? 14 ? 15 ? 16 ? 17 ? 18 ? 19 ? 20 ? 21 ? 22 ? 23 ? 24 ? 25 ? 26 ? 27 ? 28 ? 29 ? 30 ? 31 ? 32 ? 33 ? 34 ? 35 ? 36 ? 37 ? 38 ? 39 ? 40 ? 41 ? 42 ? 43 ? 44 ? 45 ? 46 ? 47 ? 48 ? 49 ? 50 ? 51 ? 52 ? 53 ? 54 ? 55 ? 56 ? 57 ? 58 ? 59 ? 60 ? 61 ? 62 ? 63 ? 64 ? 65 ? 66 ? 67 ? 68 ? 69 ? 70 ? 71 ? 72 ? mema2 ? mema1 ? mema0 ? web ? reb ? ube(gpb[1]) ? lbe(gpb[2]) ? flashcsb(gpb[3]) ? sramcsb(gpb[4]) ? iocsb0(gpb[5]) ? iocsb1(gpb[6]) ? iowait(gpb[7]) ? dig gndc ? dig vcc ? memd15 ? memd14 ? memd13 ? dig gndp ? dig vpp ? memd12 ? memd11 ? memd10 ? memd9 ? dig gndc ? dig vcc ? memd8 ? memd7 ? memd6 ? memd5 ? memd4 ? memd3 ? memd2 ? memd1 ? memd0 ? spll_gnd ? spll_vcc 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 micgs agndc vref eara earb apll vcc apll gnd txactive(gpa[0]) rxactive(gpa[1]) txdata_en(gpa[2]) txdata(gpa[3]) rxdata(gpa[4]) syncdetect(gpa[5]) dig gndc dig vcc dataclk(gpa[6]) rfreset(gpa[7]) bluerf_tck(gpa[8]) bluerf_tms(gpa[9]) bluerf_tdi(gpa[10]) bluerf_tdo(gpa[11]) dig vpp dig gndp uarttx(gpc[0]) uartrx(gpc[1]) uartrts(gpc[2]) uartcts(gpc[3]) pcmout(gpd[0]) pcmin(gpd[1]) pcmsync(gpd[2]) pcmclk(gpd[3]) dig vcc dig gndc audsclk(gpd[4]) audlrclk(gpd[5]) audout(gpd[6])
pt0137(08/04) ver:4 10 data sheet PT8R1202 pt pericom technology inc. bluetooth digital audio streaming ic ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| package diagram of fpbga notes : 1. all dimension are in millimeters. 2. ?e? represents the basic solder ball grid pitch. 3. ?m? represents the basic solder ball matrix size. and, symbol ?n? is the number of balls after depopulating. 4. ?b? is measurable at the maximum solder ball diameter after reflow parallel to primary datum -c-. 5. dimension ?aaa? is measured parallel to primary datum ?c-. 6. primary datum ?c- and seating plan e are defined by the spherical crowns of the solder balls. 7. package surface shall be matte finish charmilles 24 to 27. 8. package centering to substrate shall be 0.0760 mm maximum for both x and y direction respectively. 9. package warp shall be 0.050mm maximum. 10. substrate material base is bt resin. 11. the overall package thickness ?a? al ready considers collapse balls. 12. dimension and toleranci ng per asme y14.5-1994.
pt0137(08/04) ver:4 11 data sheet PT8R1202 pt pericom technology inc. bluetooth digital audio streaming ic ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| package diagram for tqfp notes : 1. all dimension are in millimeters. 2. dimention shown are nominal with tol. as indicated. 3. l/f : eftec 64t copper or equivalent 0.127mm (.005?) thick 4. foot length ?l? is measured at gage plane. at 0.25mm, above the seating plane.
pt0137(08/04) ver:4 12 data sheet PT8R1202 pt pericom technology inc. bluetooth digital audio streaming ic ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| i/o description off-chip memory interface the external memory port comprises a 16bit data bus(memd[15:0]) and an 20bit address bus(mema[19: 0]), thus addressing up to 2mb ytes of off-chip code or data. control signal web, reb, and multiple csb(flahscsb, sramcsb, iocsb0 and iocsb1) are provided, which make it possible to use a variety of differe nt memories, including flash memory, sram and rom. for sram access, ube and lbe sig nal support byte access and memory interface bl ock automatically handles control signals for 32bit word, 16bit half-word and 8bit b yte access of on-chip microcontroller memory operations. in standard bluetooth application, only external 256kb flash memory is required in p t8r1202. for additional bluetooth application including several bluetooth pr otocol stack which requires more data memory than internal s ram of PT8R1202, external sram is used for extended data memory of pt 8r1202 on-chip microcontroller. the access time of each device ca n be programmed and the wait cycle ranges 0 to 63 based on system clock, which is normally processor clock, that is clksys. external flash can be programmed via host interface by external host or self update by PT8R1202 on-chip risc/dsp processor. because PT8R1202 on-chip risc/dsp processor is based on harvard ar chitecture, the address map of instruction and data access is difference. following table 1. shows the instruction address map and table 2. shows the data address map. table 4. instruction address map address(24bit)* device attribute description 0x000000~0x1fffff flash read only cacheable, scratch-pad memory or non-cacheable 0x200000~0x3fffff - - reserved 0x400000~0x5fffff sram read only cacheable, scratch-pad memory or non-cacheable 0x600000~0x7fffff io0 read only cacheable, scratch-pad memory or non-cacheable 0x800000~0x9fffff io1 read only cacheable, scratch-pad memory or non-cacheable * this address space is based on byte addressing. there are a ddition extended two bits in the most significant bits(25th and 24 th), and they are used for the indication of section attribute. all instructions are checked whether they are cached in the scratch-pad memory fi rst. then, those two bits are used to check the source of that instruction fetch. ?00? indicates those section can be loaded only through on-chi p instruction cache with conventional two-way set associate policy. ?01? indicates th ose section can be loaded only se t0 region of on-chip instruct ion cache. ?10? indicates those section can be loaded only set1 region of on-chip instruction cache. ?11? indicates those section can be loaded directly from external memory without passing instruction cache. the address space of this intern al scratch-pad memory is 0xa00000~0xa0bfff f or xmem and 0xc00000~0xc0bfff for ymem. the scratch memory is divide d into four pages each size of which is 32kb with 9-bit instruction tag which consists of 3-bit section attribute and th e most significant 6-bit section address. on-chip risc processo r will check the match by full associative comparison with four tag registers of internal scratch-pad memory first. then, if that tag comparison is matched, instruction will be fetched from internal scratch-pad memory. otherwise, instruction will be fetc h through on-chip instruction cache from external flash memory region. table 5. data address map address(23bit)* device attribute description 0x000000~0x1fffff flash read/write half-word, word z instruction code memory z constant data memory z accessible by on-chip dma 0x200000~0x3fffff - - reserved 0x400000~0x5fffff sram read/write byte, half-word, word z data memory z fast fetch instruction code memory z accessible by on-chip dma 0x600000~0x7fffff io0 read/write byte, half-word, word z i/o access z accessible by on-chip dma 0x800000~0x9fffff io1 read/write byte, half-word, word z i/o access z accessible by on-chip dma 0xa00000~0xa07fff xmem0 (32kb) read/write byte, half-word, word dsp memory (14m) z data memory z scratch-pad instruction memory z smartmedia? fifo z accessible by dma 0xa08000~0xa0bfff xmem1 (16kb) read/wrtie byte, half-word, word dsp memory (14m) z data memory z scratch-pad instruction memory z smartmedia? fifo z accessible by on-chip dma 0xa0c000~0xa0ffff xmem2 (16kb) read/write byte, half-word, word z data memory z bluetooth baseband fifo, z usb fifo(0x20c000~0x20ffff) z accessible by on-chip dma 0xc00000~0xc07fff ymem0 (32kb) read/write byte, half-word, word z data memory z scratch-pad instruction memory
pt0137(08/04) ver:4 13 data sheet PT8R1202 pt pericom technology inc. bluetooth digital audio streaming ic ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| dsp memory (14m) z smartmedia? fifo z accessible by on-chip dma 0xc08000~0xc0bfff ymem1 (16kb) read/write byte, half-word, word dsp memory (14m) z data memory z scatch-pad instruction memory z smartmedia? fifo z accessible by on-chip dma 0xc0c000~0xc0ffff ymem2 (16kb) read/write byte, half-word, word dsp memory(14m) z data memory z digital stereo audio output fifo z accessible by on-chip dma * this address space is based on byte addressing. off-chip memory interface waveform diagram internal core clock (clksys) operation mode web cs (flash, sram, i/o) reb 0 mem wait cycles ube lbe mema[19:0] memd[15:0] 8bit-l read0 16bit read1 8bit-h write2 16bit write3 32bit read4 32bit write5 idle idle addr0 addr2 addr2 addr1 addr3 addr4 addr4+1 addr5 addr5+1 unknown data0 data1 data2 data3 data4 msb data4 lsb data5 msb data5 lsb operation mode web cs (flash, sram, i/o) reb 1 mem wait cycles ube lbe mema[19:0] memd[15:0] 8bit-l read0 16bit read1 32bit read4 idle 8bit-h write2 addr0 addr1 unknown data0 data1 16bit write3 idle addr3 addr4 addr4+1 data2 data3 data4 msb data4 lsb
pt0137(08/04) ver:4 14 data sheet PT8R1202 pt pericom technology inc. bluetooth digital audio streaming ic ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| off-chip memory interface read access timing without wait signal off-chip memory interface read access timing with wait signal table 6. read access timing parameter symbol min max unit read cycle time t rc 1 (7.8ns) 64 (500ns) clksys clock cycles (128mhz) read data setup time t rds 3 ns read data hold time t rdh 1 ns * rscyc, racyc, rwcyc, recyc ba sed on cycle number of clksys t rc valid read data address t rds t rdh mema[19:0] csb, reb, u/lbe memd[15:0] t rsc rscyc (0~3) racyc (1~64) t rc valid read data address t rds t rdh mema[19:0] csb, reb, u/lbe memd[15:0] t rsc rscyc (0~3) wait rwcyc (0~7) recyc (0~7)
pt0137(08/04) ver:4 15 data sheet PT8R1202 pt pericom technology inc. bluetooth digital audio streaming ic ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| off-chip memory interface write access timing without wait signal off-chip memory interface write access timing with wait signal table 7. write access timing parameter symbol min max unit write cycle time t wc 2 (15.6ns) 65 (507.8ns) clks ys clock cycles (128mhz) write control signal pulse width t cpw 1 (7.8ns) 64 (500ns) clksys clock cycles (128mhz) write address hold time from control signal t wah 1 (7.8ns) 1 (7.8ns) clks ys clock cycles (128mhz) write data output enable time t wde 0 ns write data setup time to control signal t wds 4 ns (clksys=128mhz) write data hold time from control signal t wdh 1 (7.8ns) 1 (7.8ns) clks ys clock cycles (128mhz) write data output disable time t wdd 0 ns t wc valid write data address t wdh t wdd mema[19:0] csb, web, u/lbe memd[15:0] t wds t wde t cpw t wah wscyc (0~3) whcyc (0~3) wait t wah t wsc wwcyc (0~7) wecyc (0~7) t wc valid write data address t wdh t wdd mema[19:0] csb, web, u/lbe memd[15:0] t wds t wde t cpw t wah wscyc (0~3) wacyc (1~64) whcyc (0~3) t wsc
pt0137(08/04) ver:4 16 data sheet PT8R1202 pt pericom technology inc. bluetooth digital audio streaming ic ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| bluetooth radio interface PT8R1202 supports bluerf? rxmode2/3 bluetooth radio interface with uni/bi-directi onal and jtag/dbus serial interface .pti bluetooth radio transceiver. in rxmode3, syncword correlator is located in radio transceiver, syncword detect signal feeds from external radio transceiver. in rxmode2, syncword correlation is processed in PT8R1202, syncword detect signal feed to extern al radio transceiver to timing adjustment of modem. in additional to bluerf? interface, PT8R1202 supports blueq? interface with sbi serial interface. bluerf rxmode3 ? bi - directional i/f bluerf rxmode2 ? bi - directional i/f bluerf rxmode3 radio transceive r correlato r and data extraction dc estimation demodulation bpktct l syncdetect(gpa5) bxtle n gpio(optional) btx d txdata(gpa3) bnpw r rfreset(gpa7) brcl k dataclk(gpa6) bdcl k bluerf_tck(gpa8) bnde n bluerf_tms(gpa9) bddata bluerf_tdo(gpa11) PT8R1202 registe r control i/f bluerf rxmode2 radio transceive r dc estimation demodulation bpktct l syncdetect(gpa5) bxtle n gpio(optional) btx d txdata(gpa3) bnpw r rfreset(gpa7) brcl k dataclk(gpa6) bdcl k bluerf_tck(gpa8) bnde n bluerf_tms(gpa9) bddata bluerf_tdo(gpa11) PT8R1202 registe r control i/f bluerf rxmode3 radio transceiver correlato r and data extraction dc estimation demodulation brx d rxdata(gpa4) brxe n rxactive(gpa1) btxe n txactive(gpa0) bpktct l syncdetect(gpa5) bse n gpio(optional) bxtle n gpio(optional) btx d txdata(gpa3) bpae n txdata_en(gpa2) bnpw r rfreset(gpa7) brcl k dataclk(gpa6) bdcl k bluerf_tck(gpa8) bnde n bluerf_tms(gpa9) bmos i bluerf_tdi(gpa10) bmis o bluerf_tdo(gpa11) PT8R1202 registe r control i/f bluerf rxmode2 radio transceive r dc estimation demodulation brxd rxdata(gpa4) brxe n rxactive(gpa1) btxe n txactive(gpa0) bpktct l syncdetect(gpa5) bse n gpio(optional) bxtle n gpio(optional) btx d txdata(gpa3) bpae n txdata_en(gpa2) bnpw r rfreset(gpa7) brcl k dataclk(gpa6) bdcl k bluerf_tck(gpa8) bnde n bluerf_tms(gpa9) bmos i bluerf_tdi(gpa10) bmiso bluerf_tdo(gpa11) PT8R1202 registe r control i/f bluerf rxmode3 ? uni - directional i/f bluerf rxmode2 ? uni - directional i/f blue q blueq sync_de t syncdetect(gpa5) rx_tx_data txdata(gpa3) clk_re f dataclk(gpa6) sbc k bluerf_tck(gpa8) sbs t bluerf_tms(gpa9) sbd t bluerf_tdo(gpa11) gdm1202 blue q radio transceiver dc estimation demodulation sync_de t syncdetect(gpa5) rx_tx_data txdata(gpa3) clk_re f dataclk(gpa6) bluerf_tck(gpa8) sbs t bluerf_tms(gpa9) sbd t bluerf_tdo(gpa11) PT8R1202 registe r control i/f
pt0137(08/04) ver:4 17 data sheet PT8R1202 pt pericom technology inc. bluetooth digital audio streaming ic ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| external pcm interface pcmin, pcmout, pcmclk, pcmsync carry one channel of voic e data using 8-bit a/u-law, 13-bit /14-bit/16-bit linear pcm at 8kbps. PT8R1202 generates pcmclk and pcmsync as both outputs or input, which can be programmed, and interfaces directly to pcm audio devices. pcmsync operates at fixed clock frequency of 8khz . pcmclk operates at one of two fixed clock frequencies such as 128 and 256khz. pcm interface supports both long frame sync signal and short frame sync signal. additionally, PT8R1202 supports two or four channels of 8-bit a/u-law pcm interfacing with external multi-channel codec. table 8. configuration of external pcm interface configuration supporting device pcm type frame type bit length pcmclk clock channel number qualcomm msm a, u-law l 8bit 128khz 1 motorola mc145481 a, u-law s/l 8bit 128/256khz 1 oki msm7717 a, u-law l 8bit 128/256khz 1 oki msm7704 a, u-law l 8bit 128/256khz 2(dual) 8bit a/u-law codec oki msm7705 a, u-law l 8bit 256khz 4(quad) 13bit linear pcm motorola mc145483 linear s/l 13bit 128/256khz 1, 2(volume) 14bit linear pcm oki msm7716 linear l 14bit 128/256khz 1 16bit linear pcm tbd linear s/l 16bit 128/256khz 1 pcm_clk ( 128, 256, 512, 1024khz ) msb 8bit a/u-law lsb pcm_sync(8khz) (short frame) msb 16bit linear pcm lsb msb 14bit linear pcm lsb msb 13bit linear pcm lsb pcm_sync(8khz) (long frame) 8bit 13bit 14bit 16bit 3bit vol pcm_in (sample int at falling edge) pcm_out (sample out at rising edge) msb 8bit a/u-law -1ch lsb pcm_sync(8khz) ( dual-channel ) msb 8bit a/u-law -2ch lsb msb 8bit a/u-law -1ch lsb pcm_sync(8khz) ( quad-channel ) msb 8bit a/u-law -2ch lsb 8bit-3ch 8bit-4ch
pt0137(08/04) ver:4 18 data sheet PT8R1202 pt pericom technology inc. bluetooth digital audio streaming ic ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| external audio adc/dac, spdif input interface audio adc/dac interface provides a high qua lity multi resolution(16/18/20/24-bit) digital audio connection to external audio devices. adi interface supports i2s audio fo rmat as well as optional left-justified or right-justified audio format. adi interf ace produces one 64-bit frame at the audio sample frequency using a b it clock and frame sync signal in master mode. in slave mode, adi accepts one 64-bit frame in audio dac or one 64/48-bit frame at the audio samp le frequency using external generated control signal. adi interface supports severa l audio sampling frequency up to 96-khz su ch as 32, 44.1, 48, 64, 88.2, or 96-khz, of which 256 or 384 times main clock can be generated from on-chip audio pll or external clock signal by interface mode programming. adi interface contains dual on-chip fifo which size contains maximally 2048 samples with 16-bit or 1024 samples with above 16-bit stereo audio data th rough ymem2 shared with risc/dsp processor. table 9. audio interface pin description pin name i/o type description audmclk programmable clock audio oversampled clock this clock can be programme d 256 or 384 times audlrclk audsclk programmable clock audi o serial data bit clock this clock is fixed at 64 times audlrclk in output, but can be programmed at 64 or 48 times audlrclk or uartrts in input audlrclk programmable clock audi o frame synchronization clock this clock can be programmed up to 96khz audout output serial data audio serial data used for sending playback data to dac audin input serial data audio serial data used for receiving recording data from adc spdif serial data input uartrts programmable clock audio input serial data bit clock this pin can be programmed as alternative audio serial data bit clock for audio input interface uartcts programmable clock audio input frame synchronization clock this pin can be programmed as alternative audio frame synchronization for audio input interface ms ms-1 ms-2 2 1 ls ms ms-1 ms-2 2 1 ls left right ?i 2 s interface audlrclk audout audsclk audio output : 32 audbclk audio input : any(24, 32) audbclk ms ms-1 ms-2 2 1 ls ms ms-1 ms-2 2 1 ls left right ? left-justified interface audlrclk audout audsclk audio output : 32 audbclk audio input : any(24, 32) audbclk ms ms-1 ms-2 2 1 ls ms ms-1 ms-2 2 1 ls left right ? right-justified interface audlrclk audout ausclk ms ms audio output : 32 audbclk audio input : 24, 32 audbclk
pt0137(08/04) ver:4 19 data sheet PT8R1202 pt pericom technology inc. bluetooth digital audio streaming ic ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| spdif interface the PT8R1202 supports iec-958 or spdif serial digital input or output data directly. throug h spdif interface, uncompressed audio pcm or compressed pcm can be transferred into or from the PT8R1202 in order to do wireless audio streaming solution. the function of spdif and i2s input shall be executed in the time share way. the function of spdif and i2s output can be executed in the same time. following figure shows the supported data format in the PT8R1202. usb interface usb controller in PT8R1202 is compliant usb 1.1 version. the usb functionality is executed by an usb hardware block and firmware running on v6 risc processor. this configuration allows acceleration of the intensive function processing while allowing flexibility in the implementation of higher level pr otocols over usb. usb controller in PT8R1202 supports both 12mbps high speed mode and 1.5mbps low speed mode and host and device mode programmed by firmware. the usb hardware block consists of a serial interface engine(s ie), a serial bus controller(sbc) and a v6pb bus interface. the sie performs the clock/data separation, nrzi encoding and de coding, bit stuffing and unstuffing, crc generation and checking and the serial-parallel data conversion. the sbc consists of protocol engine and a usb device with nine endpoints including endpoint0 for control, each with single or double buffered scheme . control endpoint co nsists of single 16-byte fifo for transmi t and receive, and eight endpoints consist of dual 64-byte fifos in each side, wh ich is shared through xmem2 with on-chip risc processor. four of eight endpoints are for transmit and others for r eceiving. additionally, ther e are four endpoints dedicated to isochronous operation with 1023-byte fifo located in xmem2. the sbc manages the device address, monitors the status of the transactions, manage the fifos and communicates to the processor through a set of status and control register s. the v6pb bus interface connects the seri al bus controller to the processor. z endpoint 0 (ep0) : control endpoint equipped with 16bytes single-buffered fifo z endpoint 1 (ep1) : out endpoint (control, interrupt, bulk) with 64bytes double-buffered fifo z endpoint 2 (ep2) : in endpoint (control, interrupt, bulk) with 64bytes double-buffered fifo z endpoint 3 (ep3) : out endpoint (control, interrupt, bulk) with 64bytes double-buffered fifo z endpoint 4 (ep4) : in endpoint (control, interrupt, bulk) with 64bytes double-buffered fifo z endpoint 5 (ep5) : out endpoint (control, interrupt, bulk) with 64bytes double-buffered fifo z endpoint 6 (ep6) : in endpoint (control, interrupt, bulk) with 64bytes double-buffered fifo z endpoint 7 (ep7) : out endpoint (isochronous) with 1023bytes single-buffered fifo z endpoint 8 (ep8) : in endpoint (isochronous) with 1023bytes single-buffered fifo z endpoint 9 (ep9) : out endpoint (control, interrupt, bulk) with 64bytes double-buffered fifo z endpoint 10 (ep10) : in endpoint (control, interrupt, bulk) with 64bytes double-buffered fifo z endpoint 11 (ep11) : out endpoint (isochronous) with 1023bytes single-buffered fifo z endpoint 12 (ep12) : in endpoint (isochronous) with 1023bytes single-buffered fifo preamble aux data lsb audio data msb v u c p 31 27 8 7 4 3 0 sub-frame validity user data channel status data parity bit x channel a y channel b z channel a y channel b x channel a y channel b sub-frame sub-frame frame 191 frame 0 frame 1 start of channel status block
pt0137(08/04) ver:4 20 data sheet PT8R1202 pt pericom technology inc. bluetooth digital audio streaming ic ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| PT8R1202 supports device function, hub function and host function in usb 1.1 version. specially, PT8R1202 emulates the multiple device operations simultaneously with supporting hub function. together with on-chip nand flash controller and audio dsp, PT8R1202 supports multiple function in usb dongle which in tegrates bluetooth, usb storage device and usb sound card. following list is possible configuration for multiple usb device system on a chip. table 10. recommend endpoint mapping in usb usb bus (multiple usb devices over single usb bus) bulk device iso device bulk, iso device bluetooth device driver portable storage device driver audio device driver PT8R1202 nand bulk, iso device usb hub wireless stereo headset over bluetooth bluetooth end point bluetooth usb dongle bluetooth usb dongle + usb storage device bluetooth usb dongle + usb storage device + usb sound device ep0 common control common control common control ep1(out) bt event (interrupt) bt event (interrupt) bt event (interrupt) ep2(in) bt command (control) bt co mmand (control) bt command (control) ep3(out) bt acl data (bulk) bt acl data (bulk) bt acl data (bulk) ep4(in) bt acl data (bulk) bt acl data (bulk) bt acl data (bulk) ep5(out) reserved hub hub ep6(in) reserved reserved usb audio control ep7(out) bt sco data (isoch) bt sco data (isoch) bt sco data (isoch) ep8(in) bt sco data (isoch) bt sco data (isoch) bt sco data (isoch) ep9(out) usb storage (bulk) usb storage (bulk) ep10(in) usb storage (bulk) usb storage (bulk) ep11(out) reserved reserved usb audio stream (isoch) ep12(in) reserved reserved usb audio stream (isoch)
pt0137(08/04) ver:4 21 data sheet PT8R1202 pt pericom technology inc. bluetooth digital audio streaming ic ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| uart interface uarttx, uartrx, uartrts, and uartcts form a conventional as ynchronous data serial port. the interface is designed to operate correctly when conn ected to other uart devices such as ns16550a. the signaling levels are 0v and 3.3v. the interface is programmable over a variety of b it rates. it supports many configurations such as no, even or odd parity, one or t wo stop bit, number of bit in a frame, break conditions, and hardwa re flow control on or off. the maximum uart data rates is 1.8mb/s. two-way hardware control is implemented by uartrts and uartcts. if input uartcts signal becomes high, transmission will be stopped, else it will be continued. if inte rnal uart fifo will be full, output uartrts signal becomes high, else becomes low. flash card interface PT8R1202 supports two types of flash card such as smartmed ia? flash devices and mmc or sdcard flash devices. this flash card devices are small removable cards that contain one or two n and flash devices. alternatively, the system designer can use non-removable nand flash chips. PT8R1202 supports hardware interface logic for smartmedia? devices, but only supports software firmware using gpio for mmc or sdcard. the smartm edia? electrical interface uses an 8-bit data/address bus and 6-bit control lines. PT8R1202 supports up to 4gb smartmedia? devices.
pt0137(08/04) ver:4 22 data sheet PT8R1202 pt pericom technology inc. bluetooth digital audio streaming ic ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| jtag interface PT8R1202 supports ieee1149.1 standard specification compliant in terface. this interface supports basic test commands such as extest, smaple, bypass, and idcode. beside of this, jt ag interface can be used communication channel with pti enhanced on-chip hardware debugger controller. using on-chip debugger controller, off-chip debug handler or external host can access internal peripheral device registers, external memory interface, and executes real-timing hardware debugging and monitoring of on-chip embedded risc processor. also, external host can communicate on-chip risc processor through jtag with on-chip hardware managed channel buffer. there are sixteen debug registers specified and these will be used in pti own development chip manager software, named as v6emu?. the length of instruction register in jt ag interface is 6bit and that of debug data register is 32bit. table 11. shows the summary of tap instructions supported in PT8R1202 and table 12. shows the summary of debugger registers in jtag interface. table 11. tap instructions instruction opcode description extest 0x000000 extest initi ates testing of external circuitry, typi cally board-level interconnects and off chip circuitry. extest connects the boundary-scan regi ster between tdi and tdo in the shift_dr state only. when extext is selected, all output signa l pin values are driven by values shifted into the boundary-scan register and may change only on the falling-e dge of tck in the update_dr state. also, when extest is sel ected, all system input pin states must be loaded into the boundary-scan register on the rising-edge of tck in the capture_dr state. values shifted into input latches in the boundary-scan register are ne ver used by the processor?s internal logic. sample 0x000001 sample / preload performs two functions: ? when the tap controller is in the capture-dr state, the sample instruction occurs on the rising edge of tck and provides a snapshot of the component?s normal operation without interfering with that normal operation. the in struction causes boundary-scan register cells associated with outputs to sample the value being driven by or to the processor. ? when the tap controller is in the update-dr state, the prel oad instruction occurs on the falling edge of tck. this instruction causes the tran sfer of data held in the boundary-scan cells to the slave register cells. typically the slave latched data is then applied to the system outputs by means of the extest instruction. idcode 0x011111 idcode is used in conjunctio n with the device identificat ion register. it connects the identification register between tdi and tdo in the shift_dr state. when selected, idcode parallel-loads the hard-wired identification code ( 32 bits) on tdo into the identification register on the rising edge of tck in the capture_dr state. note: the device identification register is not altered by data being shifted in on tdi. debug (private instruction) 0x10ssss debug instruction select the debugreg with address indicator ssss. ? when the tap controller is in the capture-dr state, the debug instruction occurs on the rising edge of tck and executes a snapshot of debug register addressed ssss into debugreg. ? when the tap controller is in the update-dr st ate, the debug instruction occurs on the falling edge of tck. this instruction causes the transfer of data held in deb ugreg to debug register addressed ssss. bypass 0x111111 bypass instruction select s the bypass register between tdi and tdo pins while in shift_dr state, effectively bypassing the processor?s test logic. 0 is captured in the capture_dr state. while this instruction is in effect, all other test data registers have no effect on the operation of the system. test data registers with both test and sy stem functionality perform their system functions when this instruction is selected table 12. debug interfa ce register address map address name attribute description 0x0 debug_cmd write debugger control register 0x1 debug_ctrl read debug handler control register 0x2 debug_tx read debug handler transmit register 0x3 debug_rx write debug handler receive register 0x4 debug_addr write debugger address register 0x5 debug_wdata0 (debug_cyc_cnt) write debugger write data register0(31:0) debugger instruction step count 0x7 debug_rdata0 read debugger read data register0(31:0) 0x9 debug_inst_acnt read debugger instruction cycle accumulator 0xa debug_inst_scnt read debugger instruction step cycle count 0xb debug_break_pc write debugger breakpoint pc register
pt0137(08/04) ver:4 23 data sheet PT8R1202 pt pericom technology inc. bluetooth digital audio streaming ic ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| electrical specifications absolute maximum rating symbol parameter condition min typ max unit t a storage temperature -40 150 c supply voltages : spll_vcc, apll_vcc, vcc t a = +25 c -0.4 2.1 v supply voltage : acodec_vcc -0.4 3.6 v supply voltage : vpp -0.4 3.6 v other terminal voltage -0.4 3.6 v recommended operating conditions symbol parameter condition min typ max unit t a ambient temperature -40 25 105 c vcc supply voltage vcc (to vcc_gnd)* t a = +25 c 1.62 1.8 1.98 v vpp supply voltage vpp (to vpp_gnd)* ta=+25 c 2.7 3.0 3.6** v spvcc supply voltage spll_vcc (to spll_gnd)* ta=+25 c 1.62 1.8 1.98 v apvcc supply voltage apll_vcc (to apll_gnd)* ta=+25 c 1.62 1.8 1.98 v acvcc supply voltage acodec_vcc(to acodec_gnd)* ta=+25 c 2.7 3.0 3.6 v difference between any two vcc, spll_vcc, apll_vcc terminals ta=+25 c 0.3 v * an external regulator is required for reliability
pt0137(08/04) ver:4 24 data sheet PT8R1202 pt pericom technology inc. bluetooth digital audio streaming ic ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| dc/ac specification unless otherwise noted, the specification applies for: ta=+25 c, typical conditions sym parameter condition min typ max unit digital inputs v ih logical input high 2.0 vpp v v il logical input low -0.3 0.8 v i leak input leakage current 0.5 < v in < v cc -0.5 -1 1 a digital outputs v oh logical output high 2.4 v v ol logical output low 0.4 v tri-state output leakage current -1 1 a low level max output current for mema, memd, reb, web 13.2 ma high level max output current for mema, memd, reb, web 24.8 ma low level max output current for others 6.6 ma high level max output current for others 12.4 ma usb signals (d+, d-) v di differential input sensitivity (d+) ? (d-) -0.2 0.2 v v cm differential common mode range 0.8 2.5 v v se single ended receiver threshold 0.7 1.7 v v uol output low voltage r l =1.5 k 0.3 v v uoh output high voltage r l =1.5 k 2.8 v i uoz tri-state date line leakage o < v in < 3.3 -10 10 a current consumption operating supply current of v cc under 96mhz operation 100 ma low power mode supply current of vcc under idle operation 3.5 ma sleep mode supply current of vcc 0.55 ma operating supply current of vpp 10 ma sleep mode supply current of vpp under oscillator operation 0.5 ma operating supply current of spll_vcc 3.5 ma sleep mode supply current of spll_vcc 0.35 ma operating supply current of apll_vcc 1.6 ma sleep mode supply current of apll_vcc 0.2 ma operating supply current of acodec_vcc 11.8 ma sleep mode supply current of acodec_vcc 0.12 ma system power consumption deep sleep with rtc timer operation vpp, acodec_vcc =3.0v, others all 1.8v 4.7 mw sleep with rtc timer operation vpp, acodec_vcc =3.0v, others all 1.8v 18.2 mw bt data transfer (dm5)* vpp, acodec_vcc =3.0v, others all 1.8v 41 mw bt voice connection (hv1)* vpp, acodec_vcc =3.0v, others all 1.8v 45 mw mp3 decoding from nand flash* vpp, acodec_ vcc =3.0v, others all 1.8v 111 mw mp3(128kbps) streaming from bluet ooth link* vpp, acodec_vcc =3.0v, others all 1.8v 139 mw sbc(384kbps) streaming from bluetooth link* vpp, acodec_vcc =3.0v, others all 1.8v 91 mw voip(g.723.1) call with bluetooth link* vpp, ac odec_vcc =3.0v, others all 1.8v 136 mw * the actual power consumption depends on real situation.
pt0137(08/04) ver:4 25 data sheet PT8R1202 pt pericom technology inc. bluetooth digital audio streaming ic ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| application note PT8R1202 reference configuration applications ? wireless speaker for dvd / pc surround speaker with cd quality, low-la tency audio transmission ? portable digital audio player with bluetooth streaming and storage function ? bluetooth stereo headset with combining a/v profile and headset profile ? 3-in-one multi-functions(bluetooth, usb audio, usb flash storage) usb dongle ? bluetooth usb printer adaptor with usb host function ? bluetooth handsfree with on-chip echo cancellation function ? bluetooth voip phone with on-chip speech compression function iocsb0/1 iowait mema[19:0] web,reb,ube,lbe memd[15:0] rs232 driver pcm codec (mc145483) uarttx,uartrx, uartrts,uartcts pc serial port pcmclk, pcmsync, pcmin, pcmout reset txactive(gpa0) rxactive(gpa1) txdataen(gpa2) txdata(gpa3) rxdata(gpa4) syncdetect(gpa5) dataclk(gpa6) bluerf_tck(gpa8) bluerf_tms(gpa9) bluerf_tdi(gpa10) bluerf_tdo(gpa11) 13mhz 16mhz gdm1002 xtalin xtalout xtalin reset txactive rxactive txdataen txdata rxdata syncdetect dataclk tck tms tdi tdo sramcsb audio dac (cs42l50) audsclk, audlrclk, audout, audmclk, audin, gpio(scl), gpio(sda) sm_csb,cle,ale sm_we,oe,rb sm_data[7:0] gpios gpg0(key0), gpg1(key1), gpg2(key2) sram lcd compact flash ethernet ide pc parallel port jtag_tck,jtag_tms, jtag_tdi,jtag_tdo, jtag_rst usb bluetooth radio transceiver d+ d- mmc/sd card nand flash flashcsb nor flash 1.8v ldo 3.3v ldo eara earb 32.768khz pt8r1002
pt0137(08/04) ver:4 26 data sheet PT8R1202 pt pericom technology inc. bluetooth digital audio streaming ic ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| notes pericom technology inc. email: support@pti.com.cn web site: www.pti.com.cn, www.pti-ic.com china : no. 20 building, 3/f, 481 guiping road, shanghai, 200233, china tel: (86)-21-6485 0576 fax: (86)-21-6485 2181 asia pacific : unit 1517, 15/f, chevalier commercial centre, 8 wang hoi rd, kowloon bay, hongkong tel: (852)-2243 3660 fax: (852)- 2243 3667 u.s.a. : 3545 north first street, san jose, california 95134, usa tel: (1)-408-435 0800 fax: (1)-408-435 1100 pericom technology incorporation reserves the right to make cha nges to its products or specifica tions at any time, without noti ce, in order to improve design or performance and to supply the best po ssible product. pericom technology does not a ssume any responsibility for use of any ci rcuitry described other than the circuitry embodied in pericom technology product. the company makes no representations that circuitry described herein is f ree from patent infringement or other rights, of pericom technology incorporation.


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